(1) Field of the Invention
The present invention relates to the manufacture of semiconductor memory devices in general, and in particular, to the fabrication of a flash memory cell using damascene-like structures.
(2) Description of the Related Art
A conventional memory cell, such as the electrically programmable read-only memory (EPROM) cell, usually comprises a single field effect transistor (FET) having a stacked floating gate and a control gate. A related stacked memory cell is shown in FIG. la, where source/drain regions (11) separated by channel area (15) are formed in semiconductor substrate (10). As is well-known in the art, floating gate (30) and control gate (50) are typically formed by patterning two conductively doped polysilicon layers, and the floating gate is completely surrounded by an electrically isolating dielectric, hence, its name. However, because the floating gate is formed by etching a first polysilicon layer over a thin gate oxide layer (20) grown on channel area (15) of the FET, there is usually damage done to the underlying active region of the cell. In addition, there is the problem of poly residue after the etching, which raises reliability issues. It is common practice to use highly selective etch to prevent the residue, but that also has the attendant problems of eroding and distorting the gate geometries which in turn affect the gate coupling ratio. It is disclosed in the embodiments of the present invention a method of forming a stacked gate of a flash memory cell without damaging the active regions, and also with well-defined gate profile. This will be accomplished by applying a modified damascene process to the fabrication of a flash memory cell. As it will be described later, in a damascene process, metal is deposited in a channel that has already been formed in an insulator, rather than depositing the material first on the insulator and defining, or, shaping it later by etching, as is customarily done. In the present invention, gate material, such as polysilicon, and not metal, is deposited into a damascene structure that will have been already formed.
As seen in FIG. la, floating gate (30) is separated from the substrate and the control gate by the dielectric layers (20) and (40), respectively. Control gate (50) is formed on the dielectric insulating layer (40) aligned over the floating gate, and is accessed by the peripheral circuits on the EPROM chip via word lines that interconnect the FET control gats. The control gate and floating gate are capacitively coupled through the thin dielectric layer.
In an array, the selected cells are coded (programmed) by applying a sufficiently high voltage potential between the control gate and the FET drain, resulting in the injection of hot channel electrons in the substrate through the thin gate oxide into the floating gate. Since the floating gate is well insulated, the accumulated charge is retained for an indefinite period of time thereby providing an array of coded non-volatile memory cells.
The charge stored on the floating gate shifts the threshold voltage, V.sub.t, on the programmed FET (charged FET), while the V.sub.t on the uncharged (non-programmed FET) is not shifted in value. When the memory cell on the EPROM chip is selected by the addressed decode circuit on the periphery of the EPROM chip, and a gate voltage V.sub.g is applied to the control gate having a value between the V.sub.t of the non-programmed and programmed FETs, the non-programmed FET turns on and the programmed FET does not. The conductive state (on or off) of the FET channel is then interpreted as digital binary ones or zeros.
Typically, the stored data (electrical charge) on the EPROM chip is erased by removing the chip from the equipment, and exposing it for 20 to 30 minutes to ultraviolet radiation to generate electron-hole pairs in the gate oxide and to thereby provide an electrical path to discharge the floating gate. By incorporating these floating gates in a circuit with the proper circuit design, the floating gates can be discharged (erased) by reversing the polarity of the programming voltage, allowing for the fabrication of electrically erasable programmable read-only memory (EEPROMs). And further, by providing for the simultaneous erasure of all the coded memory cells, flash EEPROMs can also be fabricated.
The double gate in the FET patterned from the two doped polysilicon layers represents a capacitive divider. It is desirable to have the threshold voltage V.sub.t as low as possible for higher density EPROM circuits. Thus, for even an uncharged floating gate, the FET appears to have a higher threshold voltage V.sub.t as viewed from the control gate than an equivalent FET would have without the floating gate. For example, a gate voltage of V.sub.2 on control gate (50) of FIG. 1a results in a low voltage V.sub.1 on floating gate (30) having a value of V.sub.1 =K.times.V.sub.2, where K=C.sub.2 /(C.sub.1 +C.sub.2) is the capacitive coupling constant, C.sub.2 is the capacitance between the control gate and the floating gate, and C.sub.1 is the capacitance between the floating gate and conducting channel (15) of the FET. To minimize the operating and programming voltages, it is desirable to have the capacitive coupling between the control gate and floating gate as large as possible, therefore C.sub.2 should be as large as possible.
Unfortunately, during the further downscaling of the minimum feature sizes on the EPROM integrate circuit to achieve much higher densities required for future EPROM chips having a reasonable size, it is necessary to reduce the area that the memory cell occupies on the chip. However, this necessarily reduces the area of the gate electrodes, and thereby reduces the capacitive coupling ratio K between the floating and control gates on a conventional prior art EPROM. This reduction in area is exacerbated by the conventional methods of forming the stacked gates, namely, by first depositing polysilicon layers and etching them. The etching usually distorts and erodes the shape and size of the intended gates. This problem can be alleviated by applying a modified damascene process as disclosed in the present invention.
The term `damascene` is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, grooves and holes in appropriate locations in the grooves are formed in an insulating material by etching, which are then filled with metal. Metal in grooves form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or grooves, are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, hole openings are also formed at appropriate places in the groove further into the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process, two insulating layers (120) and (130) are formed on a substrate (100) with an intervening etch-stop layer (125) as shown in FIG. 2a. A desired trench or groove pattern (150) is first etched into the upper insulating material (130), as shown in FIG. 2a, using conventional photolithographic methods and photoresist (140). The etching stops on etch-stop layer (125). Next, a second photoresist layer (160) is formed over the substrate, thus filling the groove opening (150), and patterned with hole opening (170), as shown in FIG. 2b. The hole pattern is then etched into the lower insulating layer (120), thus forming the dual damascene structure.
Or, the order in which the groove and the hole are formed can be reversed. Thus, the upper insulating layer (130) is first etched, or patterned, with hole (170), as shown in FIG. 2c. The hole pattern is also formed into etch-stop layer (125). Then, the upper layer is etched to form groove (150) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (120), as shown in FIG. 2d. It will be noted that the etch-stop layer stops the etching of the groove into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and groove opening are filled with metal (180), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in FIG. 2e.
It will be apparent to those skilled in the art that by forming the grooves and the holes and filling them with metal will yield more precisely formed conductive lines and contacts, and also, the problem of residue will not be an issue as in much as there is no metal etching involved. It will be shown later in the embodiments of the present invention a method of utilizing a modified damascene process in the forming of polysilicon gates in EEPROM cells with the attendant gain in capacitive coupling between the control gate and the floating gate.
Lee in U.S. Pat. No. 5,707,897 also proposes a method of forming non-volatile memory cells on EPROM devices having enhanced capacitive coupling between the control gate and the floating gate. The array of memory cells consists of a single FET having an additional floating gate. The FET is formed in a well etched into an insulating layer on the substrate surface. After forming the FET gate oxide, a polysilicon layer is patterned to form a trench-like floating ate with increased capacitive coupling. An interlevel dielectric layer is deposited. A second polysilicon layer is deposited in the well and chemical-mechanical polished back to form the control gate. The insulating layer having the wells is selectively removed.
Lightly doped source/drain areas, self-aligned to the FET gate electrodes, are implanted and after forming sidewall spacers on the gate electrodes, source/drain contacts and a buried bit lines are formed by a second implant. An insulating layer is deposited over the array of FETs having contact openings to the FET control gates. Another polysilicon layer is deposited and patterned to form the word lines. The word lines and buried bit lines are connected to the peripheral circuits to complete the EPROM chip.
Hsu, et al., of U.S. Pat. No. 5,753,525 also disclose a method of making an EEPROM cell with improved coupling ratio. The method includes forming a tunnel oxide layer on a wafer and forming floating gates on the tunnel oxide layer with the floating gate having sidewalls. Isolation regions are formed adjacent the sidewalls. A conformal ONO layer of dielectric is formed on the floating gate and sidewalls, using chemical vapor deposition (CVD). Next, a selective etch material layer is deposited on the wafer over the conformal dielectric layer. A polish stop layer is deposited on the wafer over the selective etch material layer to define an upper polishing surface above the floating gate. The exposed polish stop layer and underlying selective etch material are removed by depositing an oxide layer on the polish stop layer and then polishing the deposited layer coplanar with the polish stop layer which is an upper polishing surface above the floating gates. Exposed portions of the polish stop layer are removed to expose the selective etch layer above the floating gates and above sidewall regions adjacent the sidewalls. Then, the exposed selective etch layer is removed, exposing the conformal dielectric layer. Finally, a control gate is formed by depositing a control gate layer above the floating gate and within the sidewall region and patterning the control gate layer. The patterned control gates extend over the floating gate and along the floating gate sidewalls. The control gate-floating gate capacitor area includes the floating gate sidewalls.
On the other hand, Doan, et al., of U.S. Pat. No. 5,767,005 disclose a method for forming a floating gate semiconductor device by depositing a conductive layer into a recess over gate oxide formed on a substrate. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that the entire conductive layer except material in the recess and on the gate oxide is removed. A control gate is then formed over an insulator deposited on the floating gate. An asymmetric virtual ground EPROM cell is shown in U.S. Pat. No. 5,032,881 by Sardo, et al. The cell is a virtual ground cell in that there are no fixed connections in the array to ground potential. A method of improving the packing density of flash memories is described by Acocella in U.S. Pat. No. 5,643,813. This is accomplished by confining floating gate between regions that are planarized, thus avoiding severe topology that would otherwise exist.
In the present invention, taking advantage of the disclosed modified damascene process, the curved topology over the isolation regions are in fact exploited to increase the coupling ratio between the control gate and floating gate. Furthermore, the integrity of the stacked gate is preserved. Finally, eliminating the conventional etching step of the polysilicon layers used for the gates circumvents the problem of poly residues, as disclosed in the embodiments of the instant invention.